Dual damascene structures are well known in semiconductor integrated circuit manufacturing. A typical dual damascene structure comprises two IC levels in each of which was formed a trench or a via, which were subsequently filled with a conductor. Dual damascene technology can be used to create a multilayer interconnect in which conductors at two or more levels of the IC structure and interconnected by vias extending between the layers. A problem that is encountered in creating such structures is the need to accurately align one layer with another so that the vias connect the conductors as intended. This problem is exacerbated as feature sizes shrink.
Techniques are known to secure alignment include the define-via-first and define-trench-first methods. In the define-via-first method, often a high dielectric constant etch stop layer is used during the via etch after forming the trench. Disadvantageously, using an etch stop can increase parasitic capacitance between conductors, reducing circuit performance. In the define-trench-first method, contacts and vias are defined after the trench formation. This requires the photolithographic apparatus to have a large depth of focus. However, small depth of focus associated with current photo resist processes gives rise to difficulties in achieving desired via size and definition, as well as so-called resist scumming. Moreover, this requirement for large depth of focus becomes increasing difficult to achieve as feature sizes shrink.
Furthermore, there are intrinsic alignment problems when employing these processes. For example, misalignment of the via during photolithography may cause localized deviations in trench size where the vias are formed. Moreover, the misalignment of the via to the trench level will cause the via to be of a smaller size and an unusual shape, such as half-moon in the case of partial overlap. One possible solution is to make the trench wider than the via to account for the misalignment tolerances. However, this is inconsistent with the trend toward smaller feature sizes. Another difficulty relates to the fact that it is desirable for the vias to be of square cross-section because this increases the area, and hence decreases electrical resistance, between layers. However, attempts to make square vias from masks of square aperture generally fail when feature sizes shrink to about 0.5 micron or less. Specifically, rounded vias are produced; this effect believed to stem from photoresist surface-tension effects. This leads to vias of lower-than-desired cross-sectional area and higher series resistance than the case of square vias.